Researchers at the Indian Institute of Technology (IIT) Guwahati have created a secure and dependable integrated circuits (ICs) for faster and efficient computing.

With increasing computational demands, there is a need for application-specific processors that can outperform current CPUs. While multicore processors are being used in modern times, their computing power improvements continue to be insufficient.

"A promising technology to improve computational efficiency is hardware accelerators. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU core of the system," said Dr. Chandan Karfa, Associate Professor, Department of Computer Science & Engineering, IIT Guwahati.

"For example, visualisation processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks," Karfa added.

IIT Guwahati team emphasised on hardware acceleration specifications that are often written in high-level languages like in C/C++ and are converted to hardware code (or register transfer level or Register - Transfer Level (RTL code), in a process called High-Level Synthesis (HLS).

Due to the complex conversation process, HLS translation may introduce bugs in the design and therefore stringent validation steps are required. The RTL simulators are used to validate HLS, but these are slow and complex. The team developed simple and fast tools for HLS validation.

In addition, the team also developed a technology called HOST, which protects Integrated Circuits from IP theft during the design cycle. It has been shown to be resilient to any known attack till date.

The impact of the work is enormous because of the increasing demand for hardware accelerators in disruptive areas such as Internet-of-Things (IoT), embedded and cyber-physical systems, machine learning and image processing applications.